FOR IMMEDIATE RELEASE

Henderson Nevada, December 11th, 2000 -- Aldec, Inc., a leading supplier of HDL design entry and verification software for programmable logic devices, announced today that the new Active-HDL™ 4.2 Standard Edition will have a 300% simulation speed improvement over the previous 4.1 version, for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 includes memory resource allocation.

Simulation Kernel Improvements
With each new Active-HDL product release, Aldec is consistently enhancing it's simulation kernel and the 300% speed improvement in Version 4.2 is attributed mainly to optimizations made inside the Active-HDL simulation kernel. Since VITAL libraries are built directly into Active-HDL, they significantly speed the post place and route simulations. Active-HDL 4.2 provides designers with a powerful design and verification environment with separate stand alone compilers and simulation engines for VHDL, Verilog and mixed VHDL, Verilog and EDIF verification.

" The improvements made to the simulation kernel in Active-HDL continue to supply users the highest level of HDL simulation performance for multi-million gate FPGA design," stated Michael O'Brien, Product Marketing Manager at Aldec. "We firmly believe there is no substitute for Active-HDL available today that can match the performance and provide users with as many advanced features".

The top HDL simulation performance and easy to use features result in improved design productivity. The capability to perform a mixed VHDL, Verilog and EDIF simulation has not been provided by any other EDA tool vendor, and Aldec expects the Active-HDL 4.2 product to become the industry standard for FPGA and CPLD design verification. Mixed simulation allows designers the freedom to combine design styles and preferences as well as utilize IP Core technology for high-density, complex System-on-Chip (SoC) designs.

Memory Allocation
The memory allocation in Active-HDL 4.2 has been optimized for Verilog designs, freeing much needed resources. It has been proven that insufficient physical memory can significantly slow simulation runs due to page file swapping. Active-HDL 4.2 allows the user to estimate the memory allocation during a simulation run to ensure the system is configured with the most efficient settings. Thus, each time a design simulation is initialized, the Active-HDL Console window will break down the memory allocation and display the amount of memory used for specific simulator modules. Users are able to easily track the amount of memory resources a design is demanding and make appropriate adjustments.

Availability
Active-HDL Version 4.2 Standard Edition will be available for shipment on December 22nd, 2000 and will include a Project Manager, HDL Editor, Waveform Viewer, Testbench Generation (single process) and a choice of VHDL, Verilog or mixed language simulation kernels. The first year of maintenance is included in the product price. To request your FREE evaluation copy of Active-HDL, visit Aldec online and download at www.aldec.com.

About Aldec
Aldec has offered PC-based design entry and simulation solutions to FPGA designers for more than 15 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY) Aldec, Inc., headquartered in Henderson, Nevada, produces a universal suite of Windows based EDA tools that allow design engineers to implement their projects using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the Windows-based EDA market as the fastest growing privately held EDA supplier in the world. Additional information about Aldec is available at www.aldec.com.